PIC16F77-I/L【PDF 31/104 页】IC MCU FLASH 8KX14 A/D 44PLCC

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PIC16F7X

DS30325B-page 22

2002 Microchip Technology Inc.

2.2.2.4

PIE1 Register

The PIE1 register contains the individual enable bits for

the peripheral interrupts.

REGISTER 2-4:

PIE1 REGISTER (ADDRESS 8Ch)

Note:

Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

R/W-0

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

bit 7

bit 0

bit 7

PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit

= Enables the PSP read/write interrupt

= Disables the PSP read/write interrupt

bit 6

ADIE: A/D Converter Interrupt Enable bit

= Enables the A/D converter interrupt

= Disables the A/D converter interrupt

bit 5

RCIE: USART Receive Interrupt Enable bit

= Enables the USART receive interrupt

= Disables the USART receive interrupt

bit 4

TXIE: USART Transmit Interrupt Enable bit

= Enables the USART transmit interrupt

= Disables the USART transmit interrupt

bit 3

SSPIE: Synchronous Serial Port Interrupt Enable bit

= Enables the SSP interrupt

= Disables the SSP interrupt

bit 2

CCP1IE: CCP1 Interrupt Enable bit

= Enables the CCP1 interrupt

= Disables the CCP1 interrupt

bit 1

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

= Enables the TMR2 to PR2 match interrupt

= Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE: TMR1 Overflow Interrupt Enable bit

= Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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